This invention relates generally to the field of High Definition Television (HDTV) synchronization as in the ATSC (Advanced Television Systems Committee) HDTV (High Definition Television) standard. More particularly, in certain embodiments, this invention relates to a method and apparatus to generate SMPTE 274-1995 tri-level pulses for HDTV from an ITU-R BT.656 or ITU-R BT0.601 or similar digital video stream.
Reference is made herein to various HDTV standards including SMPTE 274-1995, which defines the specification for the timing and levels of the tri-level synchronization pulses discussed herein, and ITU-R BT.656(formerly CCIR-656), which specifies the digital video stream discussed herein. The ITU-R BT.601 specification describes a protocol that may include the Start Active Video and End Active Video signals and adds Horizontal and Vertical synchronization signals as discrete signals. The reader is directed to these publicly available documents for details of the specifications. These documents are hereby incorporated by reference herein. The present invention is applicable to other video protocols so long as the method or apparatus falls within the scope of the claims.
Digital video can be transmitted in various ways, often using the ITU-R BT.656 or ITU-R BT.601 protocol. These, and other, protocols can use digital signals to indicate the start and end of active video. It is generally the responsibility of the receiving system to generate synchronization pulses from these signals (note that provision is made for vertical and horizontal synchronization signals in the ITU-R BT.601 protocol). It is, therefore, advantageous to provide an inexpensive solution for production of these synchronization signals. In certain circumstances, it is desirable to be able to provide tri-level synchronization signals in accordance with SMPTE 274-1995 when presented with digital ITU-R BT0.656, or similar, protocol video signals.
The present invention relates generally to High Definition Television synchronization. Objects, advantages and features of the invention will become apparent to those skilled in the art upon consideration of the following detailed description of the invention.
In one exemplary embodiment consistent with the present invention, a method of generating tri-level video synchronization pulses, includes: detecting an End-Active-Video signal; responsive to detecting the End-Active-Video signal, generating a blanking signal output until a horizontal synchronization signal is received; upon receipt of the horizontal synchronization signal, generating a tri-level low signal output until the end of the horizontal synchronization signal is detected; upon detecting the end of the horizontal synchronization signal, generating a tri-level high signal output and starting a pixel counter; upon counting a predetermined number of pixel times, generating a blanking signal; detecting a start-of-video signal; upon detecting the Start-Active-Video signal, inspecting for a video synchronization signal; and if the inspecting determines a lack of a vertical synchronization signal, passing an analog video output until detection of a next End-Active-Video signal.
In another exemplary embodiment consistent with the present invention, an apparatus that generates tri-level synchronized video as an output on receipt of a digital video stream input includes a digital to analog converter that converts the digital video stream to a standard analog video signal having an active video portion, a vertical synchronization pulse and a horizontal synchronization pulse. A pixel counter is provided. A circuit coupled to the digital to analog converter generates the output signal by providing active video as the output during periods of active video in the standard analog video signal. The circuit also produces a negative synchronization signal level as the output during a duration of receipt of the horizontal synchronization pulse. The circuit is also coupled to the pixel counter and starts the pixel counter and generates a positive synchronization signal level as the output for a predetermined period as counted by the pixel counter immediately following the horizontal synchronization pulse. The circuit further produces a negative synchronization signal level as the output during a duration of receipt of the vertical synchronization pulse. The circuit also produces a blanking level as the output at other times.
The above summaries are intended to illustrate exemplary embodiments of the invention, which will be best understood in conjunction with the detailed description to follow, and are not intended to limit the scope of the appended claims.